ST and Synopsys authors report full-chip SPICE verification of a design exceeding 100 million transistors
An STMicroelectronics and Synopsys DAC 2025 presentation reports full-chip SPICE simulation of a design exceeding 100 million transistors with PrimeSim XA. The authors describe finding current-consumption and functional issues in the presented case. This preserves the customer/vendor presentation modality and does not generalize the result to all ST designs.
Evidence
Detection of Functional and Current Related Bugs in SoC through Full Chip SPICE Simulations (FCS) ↗
The official DAC 2025 record identifies ST and Synopsys authors and describes the greater-than-100-million-transistor PrimeSim XA case and reported current and functional findings.