ST authors report voltage-aware RNM and UPF verification of an SRAM subsystem

An STMicroelectronics DVCon Europe 2025 paper reports a voltage-aware SRAM verification flow using SystemVerilog real-valued supply modeling and UPF supply-net types for retention memory and bias-generator behavior. For the presented case, the paper contrasts roughly two to three hours of SPICE simulation with 10 to 12 seconds in the digital flow. It also states limitations including PVT representation and simulator-specific UPF behavior.