STMicroelectronics posts a student role for PMIC top-level verification and analog behavioral models

STMicroelectronics posted a Master Thesis / Working Student Mixed-Signal Modelling and Design Verification role in Munich. The Power Management IC Design Verification Team assigns IC top-level verification, verification-flow development and analog behavioral models, with IEEE/Accellera standards and EDA reference flows. The qualifications include Verilog/SystemVerilog, Python, analog circuits and Cadence flows, with Virtuoso SKILL as a plus. The official JobPosting metadata identifies February 16 as datePosted for job 10540; the role does not identify a particular RNM implementation or a completed automation result.