Texas Instruments authors report specification-driven AMS testbench and RTL generation
A DVCon 2014 paper by Texas Instruments authors reports a specification-driven flow that automatically generated mixed-signal testbench elements, RTL, assertions, and results infrastructure. In a power-management case study, the authors say the approach enabled analog IP-level SPICE simulation almost three months earlier than comparable prior executions within an approximately twelve-month development cycle.
Evidence
Automated Correct-by-Construct Methodology for RTL Design and AMS Test Bench Generation ↗
DVCon's record describes the Texas Instruments specification-driven RTL and AMS testbench-generation methodology.
Automated Correct-by-Construct Methodology — paper ↗
The paper details generated testbench, RTL, assertion, and results infrastructure and reports the timing outcome for its power-management case.