Texas Instruments

Last researched 2026-10-1523 indexed events

Public events shown here describe observable source material, not total internal activity.

202620252024202320212020–2014

Texas Instruments

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Sep 25, 2026

Texas Instruments battery-charging role calls for RNM models, analog checkers and mixed-signal regressions

A Texas Instruments Battery Charging Products job posting describes AMS verification of battery-management ICs. Its responsibilities include Verilog-A/AMS and wreal RNM behavioral models for top-level simulation, testbenches combining schematics, models and RTL, analog checks during simulation and after processing, RTL and gate-level regressions, and functional coverage through tape-out. UVM, scripting and interest in AI-based verification automation are preferred qualifications. A preserved copy identifies Santa Clara requisition 25018210 and a September 25, 2026 posting timestamp.

Sep 3, 2026

Texas Instruments internship listing includes analog functional coverage, random stimuli and chip-level timing checks

A University of Pittsburgh recruiting job posting dated September 3 advertises a Texas Instruments Design Verification Engineering internship. The employer description includes SystemVerilog coverage for voltages, currents and real values alongside digital coverage, constrained-random analog stimulus and automatic result checking. It also assigns RTL and gate-level simulations with SDF for timing between analog and digital circuits, regression scripting, verification planning and improvements to verification methods.

Jul 28, 2026

TI authors present ANA-MODELGEN for analog behavioral-model generation and SPICE-based validation

The DAC 2026 program lists ANA-MODELGEN by Aadhar Sharma and Texas Instruments coauthors. Its abstract describes automated generation of analog IP behavioral models and validation testbenches, with equivalence checks against SPICE references. The authors report use in production SoC verification flows and improvements in execution speed and functional coverage. This records the presented method and author-reported application; the public abstract does not establish use of an LLM or disclose independently verified results. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.

Jul 27, 2026

TI authors report using UVM-MS analog VIP for mixed-signal verification

A Texas Instruments DAC 2026 presentation reports a UVM-MS-based flow in which verification components drive and monitor analog signals without traditional connect modules. The authors describe reusable analog VIP and report improvements in simulation runtime and verification coverage for the presented use cases. The record supports this reported TI application, not universal adoption across the company. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.

Jun 22, 2026

Texas Instruments posts AMS verification role for a Bengaluru high-voltage power team

Texas Instruments posted an AMS verification engineer/lead role describing a high-voltage power team being built in Bengaluru for AC/DC controllers, isolated DC/DC converters, and GaN-integrated power stages. The role calls for SV-RNM and Verilog-AMS wreal/electrical models, system-level AMS tests, SystemVerilog/UVM testbenches, assertions and coverage, methodology development, and participation in post-silicon validation and debug.

May 21, 2026

TI advertises AI/ML-assisted analog circuit creation and design-methodology adoption

Texas Instruments posted Bengaluru role 25010677, Analog Circuit Design Engineer – AI/ML methodology. It assigns analog IC definition, modeling and schematic design, plus use of AI/ML-enabled tools and flows to accelerate development and create novel circuits. The engineer is also to drive adoption of those methods across product teams. Example circuit experience includes references, ADCs/DACs, amplifiers, oscillators and power-management blocks. This is a hiring mandate beyond device sizing alone; it does not demonstrate autonomous topology generation or measured design improvements.

Aug 3, 2025

TI intern reports SV-RNM testbench work during a Bangalore placement

Yashaswini Mudda publicly reported completing a two-month Analog Design Verification internship at Texas Instruments in Bangalore. Her account describes SystemVerilog verification and testbench-flow automation, UVM exposure, work involving RC/LC and glitch filters and analog multiplexers, and SV-RNM logic for handling multiple testbench drivers without contention. She names Balaji Ammineni as manager and Mrinav Saxena as mentor. This is a participant’s report of a completed placement, not an independently measured result or company-wide methodology claim; the date is the post’s publication, not a reconstructed internship start or end.

Jun 25, 2025

TI authors present an analog assertion and coverage toolbox for SPICE and behavioral models

A Texas Instruments DAC 2025 presentation describes an Analog Assertion and Coverage Toolbox that checks range, frequency, ramp, and glitch behavior and identifies stimulus gaps across SPICE and behavioral-model verification. The record supports the presented checker and coverage workflow; it does not establish use on every TI program.

Jun 23, 2025

TI and Cadence authors report an EEnet analog test-bus verification method

A Texas Instruments and Cadence DAC 2025 presentation reports an EEnet-based analog test-bus method for checking voltage, current, loading, and coupling behavior. The authors describe using the real-number abstraction to reduce reliance on AMS simulation for the presented verification tasks. This is a reported customer/vendor method, not a claim that EEnet replaces circuit-level verification.

Apr 10, 2025

A TI patent publication describes machine-learning-assisted generation of real-number models

U.S. patent application US20250117560A1, assigned to Texas Instruments, describes obtaining analog-simulation logs, training a neural network, deriving a mathematical transfer function, and producing a SystemVerilog-compatible simulation kernel for real-number modeling. This Event records a published patent disclosure; publication does not establish product implementation, internal deployment, or the scope of any deployed flow.

Sep 2024

TI authors report adaptive Verilog-AMS glitch checkers for earlier silicon-bug detection

A Texas Instruments DVCon India 2024 paper reports a compact Verilog-AMS checker and assertion library for adaptive detection of kickback and frequency glitches across SPICE and behavioral-model verification. The paper describes automated checker insertion and execution-flow optimization. The word intelligent appears in the paper title, but the supported implementation is an adaptive checker flow rather than a demonstrated generative-AI system.

Mar 4, 2024

Accellera releases Verilog-AMS 2023 under working-group chair Peter Grove of Renesas

Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.

Dec 21, 2023

TI patent publications disclose machine-learning methods for circuit verification and debug

Two U.S. patent applications assigned to Texas Instruments disclose complementary machine-learning techniques for analog or hybrid analog/digital integrated circuits. US20230409789A1 describes learning from simulated signal values and comparing predicted outputs with actual IC outputs for validation; US20230409790A1 describes inverse models that infer inaccessible internal signals or state-machine states from top-level inputs and outputs for debug. The documents also describe simulation-test selection using coverage metrics. These are patent disclosures, not evidence of product implementation or a deployed verification service.

Apr 6, 2023

TI authors evaluate machine-learning techniques for analog waveform prediction

A Texas Instruments ISQED 2023 paper evaluates a machine-learning behavioral-model method for time-domain waveform prediction using feature extraction, waveform segmentation, and circuit partitioning. In an operational-amplifier proof of concept, the authors report an average output-prediction signal-to-noise ratio of 32 dB. The result is an evaluated proof of concept, not evidence of production deployment.

2021

TI presenter runs an actual C++ ATE program in analog fault simulation

A CadenceLIVE presentation by TI's Jun Yan describes running C++ automatic-test-equipment test logic in analog fault simulation through the SystemVerilog DPI-C interface. The flow runs faults at sub-block level, parses simulation logs, presents pass-or-fail results in the Cadence environment, and is described as a joint effort among design verification, ATE, and design teams.

2021

TI authors report an EEnet charge-pump regulator model checked against schematic load steps

Texas Instruments authors present a SystemVerilog EEnet model of a charge-pump regulator that represents voltage, current, and resistance and includes analog impedance interactions. The poster reports matching the schematic at 1 mA, 2 mA, 3 mA, and 4 mA load-current steps, a model runtime of 10.36 seconds, and a tenfold speedup over the schematic simulation used for comparison.

2019

Texas Instruments authors report EEnet loading models for digital mixed-signal power verification

A DVCon 2019 paper by Texas Instruments authors describes using a SystemVerilog user-defined EEnet to model voltage, current, and resistance loading in power-regulation verification. The UVM-based flow randomized supplies, loads, and system states, supported reusable DMS and AMS environments, and extended verification to loading effects that simple voltage-only real-number interfaces could not represent.

2017

TI authors report schematic-bound analog assertions and machine-learning-guided PVT exploration

Two TI-authored 2017 papers report methods for analog and mixed-signal verification. One binds assertions directly to electrical ports in a schematic; the other applies support vector machines and active learning to adaptively explore process, voltage, and temperature space for coverage and worst-case conditions.

2016

TI authors propose a handoff from schematic annotations to analog functional coverage

A TI-authored paper proposes an Analog Coverage Collector through which analog designers mark internal schematic and device threshold information for use by chip-level verification engineers. The paper describes turning that information into top-level covergroups and coverage data to coordinate analog design and verification work.

2016

Texas Instruments and Cadence authors report CPF-driven low-power mixed-signal verification

A DVCon 2016 paper by Texas Instruments and Cadence authors reports applying Common Power Format power intent to a complex industrial mixed-signal SoC. The flow generated power-smart interface elements, matched results from the authors' traditional inherited-interface-element method, and reduced the reported setup time from several weeks to less than two days.

2014

Texas Instruments and Cadence authors report automating supply-aware AMS interface handling

A DVCon 2014 paper by Texas Instruments, IIT, and Cadence authors compares connect-module and interface-element methods for analog/mixed-signal boundaries and describes automation for true supply sensitivity. The authors state that the methods were applied on several commercial mixed-signal SoCs and present practical tradeoffs and guidelines for automating supply-sensitive interface handling.

2014

Texas Instruments authors report specification-driven AMS testbench and RTL generation

A DVCon 2014 paper by Texas Instruments authors reports a specification-driven flow that automatically generated mixed-signal testbench elements, RTL, assertions, and results infrastructure. In a power-management case study, the authors say the approach enabled analog IP-level SPICE simulation almost three months earlier than comparable prior executions within an approximately twelve-month development cycle.

2014

TI authors report wreal and UVM methods in two mixed-signal SoC case studies

Two TI-authored 2014 papers report mixed-signal SoC verification using higher-level analog abstractions. One describes wreal models and digital-regression reuse on a 45 nm secure SoC, including functional and design-for-test integration issues; the other describes a UVM environment for an RF transceiver SoC using wreal and Verilog-AMS models, constrained-random stimulus, assertions, coverage, and a MATLAB reference-model checker.