TI authors report wreal and UVM methods in two mixed-signal SoC case studies
Two TI-authored 2014 papers report mixed-signal SoC verification using higher-level analog abstractions. One describes wreal models and digital-regression reuse on a 45 nm secure SoC, including functional and design-for-test integration issues; the other describes a UVM environment for an RF transceiver SoC using wreal and Verilog-AMS models, constrained-random stimulus, assertions, coverage, and a MATLAB reference-model checker.
Evidence
Efficient SoC-Level Mixed-Signal Frontend Verification Using Wreal Models ↗
TI-authored 2014 case study on wreal-based frontend verification and digital-regression reuse for a 45 nm secure SoC.
Advanced Functional Verification Methodology Using UVM for Complex DSP Algorithms in Mixed-Signal RF SoCs ↗
TI-authored 2014 paper on a UVM environment with wreal and Verilog-AMS models, assertions, coverage, and MATLAB-based checking for an RF transceiver SoC.