Texas Instruments and Cadence authors report CPF-driven low-power mixed-signal verification
A DVCon 2016 paper by Texas Instruments and Cadence authors reports applying Common Power Format power intent to a complex industrial mixed-signal SoC. The flow generated power-smart interface elements, matched results from the authors' traditional inherited-interface-element method, and reduced the reported setup time from several weeks to less than two days.
Evidence
A Holistic Approach to Low-Power Mixed-Signal Design Verification Using Power Intent ↗
DVCon's record identifies the Texas Instruments and Cadence industrial case study using power intent for mixed-signal verification.
A Holistic Approach to Low-Power Mixed-Signal Design Verification Using Power Intent — paper ↗
The paper documents CPF-generated interface handling, its comparison with an inherited-interface flow, and the reported setup-time reduction.