TI authors report schematic-bound analog assertions and machine-learning-guided PVT exploration
Two TI-authored 2017 papers report methods for analog and mixed-signal verification. One binds assertions directly to electrical ports in a schematic; the other applies support vector machines and active learning to adaptively explore process, voltage, and temperature space for coverage and worst-case conditions.
Evidence
Assertion-Based Verification for Analog and Mixed-Signal Designs ↗
TI-authored 2017 paper on binding assertions to schematic electrical ports for analog and mixed-signal verification.
Machine Learning-Based PVT Space Coverage and Worst-Case Exploration in Analog and Mixed-Signal Design Verification ↗
TI-authored 2017 work applying support vector machines and active learning to PVT coverage and worst-case exploration.