TI intern reports SV-RNM testbench work during a Bangalore placement

Yashaswini Mudda publicly reported completing a two-month Analog Design Verification internship at Texas Instruments in Bangalore. Her account describes SystemVerilog verification and testbench-flow automation, UVM exposure, work involving RC/LC and glitch filters and analog multiplexers, and SV-RNM logic for handling multiple testbench drivers without contention. She names Balaji Ammineni as manager and Mrinav Saxena as mentor. This is a participant’s report of a completed placement, not an independently measured result or company-wide methodology claim; the date is the post’s publication, not a reconstructed internship start or end.