Texas Instruments internship listing includes analog functional coverage, random stimuli and chip-level timing checks
A University of Pittsburgh recruiting job posting dated September 3 advertises a Texas Instruments Design Verification Engineering internship. The employer description includes SystemVerilog coverage for voltages, currents and real values alongside digital coverage, constrained-random analog stimulus and automatic result checking. It also assigns RTL and gate-level simulations with SDF for timing between analog and digital circuits, regression scripting, verification planning and improvements to verification methods.
Evidence
Texas Instruments: Design verification internship, MS/PhD (25017546) ↗
Official TI application for the graduate design-verification internship; the employer description is also available in the university recruiting listing.
Texas Instruments DV internship — University of Pittsburgh recruitment listing ↗
Employer-supplied description on the university board, where recruitment began September 3, 2026. The Event uses this board date, not an inferred first employer publication. It explicitly covers analog functional coverage, constrained-random analog stimulus and RTL/gate+SDF checks.