THine and Siemens authors report AI-accelerated four-sigma phase-interpolator verification
A THine Electronics and Siemens DAC 2025 presentation reports AI-accelerated four-sigma verification for 8×8 phase interpolators across 64 process modes. The authors contrast thousands of guided simulations with at least ten million brute-force samples and report a 100× simulation-count reduction for the presented case. The metric is specific to this customer/vendor study.
Evidence
Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations ↗
The official DAC 2025 record identifies THine and Siemens authors and describes the 8×8 phase-interpolator, 64-process-mode, four-sigma case and its reported 100× simulation-count reduction.