Xilinx authors report combining generated real-number models, Octave, and UVM for AMS verification
A DVCon 2015 paper by Xilinx authors describes a mixed-signal verification flow combining automatically generated netlist real-number models, Octave signal processing, and a UVM environment with random stimulus and coverage. In one reported analog-multiplexer case, handwritten model content was limited to 10% of modules and 4% of lines; the paper also reports direct Octave FFT integration running 1.58x faster than its file-based comparison.
Evidence
Comprehensive AMS Verification Using Octave, Real Number Modelling and UVM ↗
DVCon's record identifies John McGrath, Patrick Lynch, and Ali Boumaalif as the Xilinx authors of the paper on generated real-number models, Octave analysis, and UVM verification.
Comprehensive AMS Verification Using Octave, Real Number Modelling and UVM — paper ↗
The paper identifies Patrick Lynch as a Xilinx author and documents the model-generation proportions, Octave integration, UVM environment, functional coverage, and FFT timing comparison.