TU Wien's repository made available Augusto Mafra and Haniel Barbosa's FMCAD paper on formal verification of SystemVerilog RNM by extending Yosys and Pono. The study uses 31 benchmarks: 17 public GPL-3.0 benchmarks and 14 built from proprietary Cadence models/testbenches. It compares real-arithmetic and IEEE floating-point SMT interpretations, whose semantics can produce different verification results. The v2.0.5 public implementation provides benchmarks, results and fixed revisions of Yosys, Pono and smt-switch. This is a research flow, not a claimed Jasper product feature; September 2 dates the paper's repository availability.