Infineon and Mentor authors report UPF-based power-aware mixed-signal verification of a sensor SoC
A DVCon 2014 paper by Infineon and Mentor Graphics authors reports applying UPF with RTL and SPICE content to power-aware mixed-signal verification of a tire-pressure-monitoring sensor SoC. The paper says the flow exposed power blackouts, sequencing errors, missing level shifters, and incorrect isolation polarity before gate-level verification.
Evidence
Power-Aware Verification in Mixed-Signal Simulation ↗
DVCon's record identifies the Infineon and Mentor Graphics power-aware mixed-signal verification presentation.
Power-Aware Verification in Mixed-Signal Simulation — paper ↗
The paper documents the UPF, RTL, and SPICE flow, its sensor-SoC context, and the classes of power-intent defects it reported.