Infineon authors extend svreal checks and FPGA debug for fixed-point mixed-signal models
A DVCon Europe paper by Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker describes svreal extensions that detect range violations and precision loss in simulation by comparing fixed-point calculations with a shadow SystemVerilog real representation. Its Integrated Fixedpoint Analyzer interprets fixed-point signal values during FPGA debug. A buck-converter model illustrates the flow between host simulation and FPGA emulation.
Evidence
Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework ↗
The official DVCon archive identifies the authors and the 2024 Europe conference year.
svreal fixed-point checks and FPGA debug — DVCon Europe paper ↗
The paper describes simulation checks for range and precision, a shadow real representation, ILA/VIO-based fixed-point interpretation, and the buck-converter example. Ordinary SystemVerilog real is used in host simulation; the FPGA uses a synthesizable representation.