Gabriel Rutsch

3 indexed events

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202420212020

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2024

Infineon authors extend svreal checks and FPGA debug for fixed-point mixed-signal models

A DVCon Europe paper by Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker describes svreal extensions that detect range violations and precision loss in simulation by comparing fixed-point calculations with a shadow SystemVerilog real representation. Its Integrated Fixedpoint Analyzer interprets fixed-point signal values during FPGA debug. A buck-converter model illustrates the flow between host simulation and FPGA emulation.

Aug 4, 2021

Stanford and Infineon authors publish an open-source framework for mixed-signal FPGA emulation

Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, and Mark Horowitz published a framework combining msdsl model generation, svreal synthesizable fixed- and floating-point representations, and anasymod FPGA build and control automation. The paper demonstrates a DragonPHY receiver, a firmware-controlled flyback converter, and an NFC-powered chip. Stanford dates publication to August 4, 2021; the TCAD journal issue is dated July 2022.

2020

Infineon and Stanford authors report FPGA prototypes for mixed-signal magnetic sensors

A DVCon Europe paper led by Gabriel Rutsch reports two FPGA prototypes for automotive magnetic sensors, using msdsl to generate synthesizable analog functional models and anasymod for FPGA build and control. One prototype supports real-time hardware-in-the-loop and customer integration; the other accelerates regression testing. The paper describes their use across product definition, verification, and design-in.