Stanford and Infineon authors publish an open-source framework for mixed-signal FPGA emulation
Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, and Mark Horowitz published a framework combining msdsl model generation, svreal synthesizable fixed- and floating-point representations, and anasymod FPGA build and control automation. The paper demonstrates a DragonPHY receiver, a firmware-controlled flyback converter, and an NFC-powered chip. Stanford dates publication to August 4, 2021; the TCAD journal issue is dated July 2022.
Evidence
Stanford AHA: Improved Validation publications ↗
Stanford's project bibliography dates this paper, DOI 10.1109/TCAD.2021.3102516, to August 4, 2021.
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs — IEEE CEDA ↗
The publisher's society page describes msdsl, svreal, anasymod, the three applications, and the July 2022 TCAD issue. svreal supplies synthesizable numerical representations, not direct synthesis of ordinary SystemVerilog real variables.
Framework publication — Technical University of Munich research record ↗
The institutional publication record identifies the authors, Stanford and Infineon affiliations, DOI, and July 2022 journal issue.