Microchip and Siemens authors report selective-SPICE digital-top verification with RTL and UPF
A Microchip and Siemens DAC 2026 presentation reports a digital-on-top mixed-signal flow combining selected SPICE blocks with RTL and UPF power intent. The presentation describes AI-accelerated Solido analysis and reports more than 22× acceleration for the presented case. This preserves the customer/vendor presentation modality and does not imply the result applies to every Microchip design.
Evidence
Comprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification Methodology ↗
The official DAC 2026 record identifies Microchip and Siemens authors and describes the selective-SPICE, RTL, UPF, and AI-accelerated flow with a reported greater-than-22× result.