TI presenter runs an actual C++ ATE program in analog fault simulation
A CadenceLIVE presentation by TI's Jun Yan describes running C++ automatic-test-equipment test logic in analog fault simulation through the SystemVerilog DPI-C interface. The flow runs faults at sub-block level, parses simulation logs, presents pass-or-fail results in the Cadence environment, and is described as a joint effort among design verification, ATE, and design teams.
Evidence
Check Analog Fault Simulation with Actual ATE Program ↗
CadenceLIVE 2021 program entry and abstract for Jun Yan's TI presentation on connecting an actual C++ ATE program to analog fault simulation.