Jun Yan

2 indexed events

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20232021

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2023

Renesas authors report automated model-versus-schematic testbenches across four PLL abstractions

A Renesas-authored paper compares AMS, open-loop RNM, closed-loop RNM without EEnet, and closed-loop RNM with EEnet representations of a PLL. It reports generating model testbenches from spreadsheet and symbol data with SKILL, a two-DUT mode for model-versus-schematic or model-versus-model comparison, and SystemVerilog stimulus and checkers alongside a Verilog-AMS hardware module.

2021

TI presenter runs an actual C++ ATE program in analog fault simulation

A CadenceLIVE presentation by TI's Jun Yan describes running C++ automatic-test-equipment test logic in analog fault simulation through the SystemVerilog DPI-C interface. The flow runs faults at sub-block level, parses simulation logs, presents pass-or-fail results in the Cadence environment, and is described as a joint effort among design verification, ATE, and design teams.