Aadhar Sharma

5 indexed events

Public technical and organizational events indexed by this site.

202620252024

JavaScript is required for Timeline filtering. Every Event remains available in the chronological Events view.

Jul 28, 2026

TI authors present ANA-MODELGEN for analog behavioral-model generation and SPICE-based validation

The DAC 2026 program lists ANA-MODELGEN by Aadhar Sharma and Texas Instruments coauthors. Its abstract describes automated generation of analog IP behavioral models and validation testbenches, with equivalence checks against SPICE references. The authors report use in production SoC verification flows and improvements in execution speed and functional coverage. This records the presented method and author-reported application; the public abstract does not establish use of an LLM or disclose independently verified results. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.

Jul 27, 2026

TI authors report using UVM-MS analog VIP for mixed-signal verification

A Texas Instruments DAC 2026 presentation reports a UVM-MS-based flow in which verification components drive and monitor analog signals without traditional connect modules. The authors describe reusable analog VIP and report improvements in simulation runtime and verification coverage for the presented use cases. The record supports this reported TI application, not universal adoption across the company. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.

Jun 25, 2025

TI authors present an analog assertion and coverage toolbox for SPICE and behavioral models

A Texas Instruments DAC 2025 presentation describes an Analog Assertion and Coverage Toolbox that checks range, frequency, ramp, and glitch behavior and identifies stimulus gaps across SPICE and behavioral-model verification. The record supports the presented checker and coverage workflow; it does not establish use on every TI program.

Jun 23, 2025

TI and Cadence authors report an EEnet analog test-bus verification method

A Texas Instruments and Cadence DAC 2025 presentation reports an EEnet-based analog test-bus method for checking voltage, current, loading, and coupling behavior. The authors describe using the real-number abstraction to reduce reliance on AMS simulation for the presented verification tasks. This is a reported customer/vendor method, not a claim that EEnet replaces circuit-level verification.

Sep 2024

TI authors report adaptive Verilog-AMS glitch checkers for earlier silicon-bug detection

A Texas Instruments DVCon India 2024 paper reports a compact Verilog-AMS checker and assertion library for adaptive detection of kickback and frequency glitches across SPICE and behavioral-model verification. The paper describes automated checker insertion and execution-flow optimization. The word intelligent appears in the paper title, but the supported implementation is an adaptive checker flow rather than a demonstrated generative-AI system.