Steven Holloway

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20252023

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Jul 1, 2025

Renesas engineer presents a concrete UVM-MS DAC verification component

At Verification Futures UK 2025, Renesas engineer Steve Holloway presented a concrete example of creating a DAC verification component using the new UVM-MS methodology. The published session description identifies the verification-component architecture and code snippets as key content. This is a public UVM-MS implementation example from a Renesas engineer, not evidence of company-wide or product-wide deployment.

Jun 22, 2023

Renesas engineers present an MS Bridge submission to the Accellera UVM-AMS Working Group

At Verification Futures UK 2023, Renesas engineers Peter Grove and Steven Holloway presented a submission to the Accellera UVM-AMS Working Group showing how an MS Bridge module could apply UVM to both AMS and DMS verification. The presentation covered simulator initialization and synchronization, stimulus and monitoring differences, a known limitation and possible solutions, and application to a mixed-signal block. The speakers said the presentation and example code had been shared with the EDA community to feed into a working-group white paper and cautioned that the implementation was not final before an official UVM-AMS release.